Kakadu Software Ltd. has developed several FPGA HTJ2K encoders, with the following properties:
- Flexible resolution support (SD/HD/4K/8K) – from 256×8 to 8192×4320
- Flexible sampling support including 4:4:4, 4:2:2, 4:2:0 and 4:4:4:4
- Flexible bitdepth support 8-16-bits per component
- SD and HD 4:2:2 interlace is supported
- Utilizes a low-latency, low-memory, all-on-chip-memory design with no need for off-chip memory
- Advanced designs can use more memory resources to improve rate control and bitrate efficiency while maintaining low-latency.
- Supports irreversible 9/7 and irreversible 5/3 wavelet filters
- Supports 2-3 vertical wavelet filters and 5 horizontal wavelet filters
Demo encoder designs are available for evaluation on the AMD Zync UltraScale+ MPSoc ZCU102 [1] and ZCU106 [2] development boards, that include HDMI input and and transmission via Ethernet using either 1GbE or 10GbE SFP-to-RJ45 adapters. The demo design uses Ethernet transmission via IETF RFC 9828 RTP packetization [3].
The demo encoder designs were demonstrated in the 4K/60 4:4:4 configuration operating in the AMD booth at ISE 2025 [4] and ISE 2024 [5].
For more information about the encoder designs or to request a demonstration design contact info@kakadusoftware.com
References:
[1] https://www.amd.com/en/products/adaptive-socs-and-fpgas/evaluation-boards/ek-u1-zcu102-g.html
[2] https://www.amd.com/en/products/adaptive-socs-and-fpgas/evaluation-boards/zcu106.html
[3] https://datatracker.ietf.org/doc/rfc9828/